1. Field of the Invention
The present invention concerns design of integrated circuits (ICs) and particularly relates to use of metal layer dependent attributes in a technology-independent description of an IC design.
2. Description of the Related Art
FIG. 1 provides a simplified cross-sectional view of a typical integrated circuit chip (or die) 50. As shown in FIG. 1, chip 50 includes a semiconductor substrate 59, metal layers 51 to 54, electrically insulating layers 56, and passivation layer 58. Semiconductor substrate 59, which is typically polysilicon, is used for forming the transistors and other electronic devices and may also be used for routing some of the electrical connections between these devices. However, wire routing occupies substrate space which otherwise could be used for the electronic devices. As a result, ordinarily only the shorter electrical connections are formed on substrate 59. For the remainder of the connections, metal layers 51 to 54 are provided.
Metal layers 51 to 54 may be formed from any of a variety of materials including aluminum, copper or an electrically conductive alloy. Typically, two to four metal layers are formed on top of substrate 59. By routing wires in the metal layers 51 to 54, electrical connections can be made without using valuable space on substrate 59. Between metal layers 51 and 52, 52 and 53, and 53 and 54, and between metal layers 51 and substrate 59 is an electrically insulating layer 56, which typically is formed as an oxide film. Connections between any of metal layers 51 to 54 and semiconductor substrate 59 are made using interlayer holes called vias. Passivation layer 58 functions to prevent the deterioration of the electrical properties of the die caused by water, ions and other external contaminants, and typically is made of a scratch-resistant material such as silicon nitride and/or silicon dioxide.
Currently, systems containing hundreds of thousands or millions of interconnected transistors and other basic electronic devices can be implemented on the semiconductor substrate of a single IC chip. Each such electronic device and wire, when viewed in relation to the other components in the IC, must satisfy a variety of electrical and physical requirements. In order to produce such complicated designs in a timely and cost efficient manner, a highly structured multi-phase design cycle has evolved. A conventional design cycle generally includes production of an IC design specification for a desired system, generation of a technology-independent description of the system, synthesis of a gate-level description of a system based on the technology-independent description, gate-level verification and physical design. The IC design specification describes the system at a high level of abstraction. The technology-independent description describes a processing scheme, together with related timing considerations, which will perform according to the design specification. Gate-level synthesis selects specific electronic components from a technology library and specifies wire connections between those components so as to implement the processing set forth in the technology-independent description. Gate-level verification verifies feasibility of the gate-level design. Finally, the physical design phase performs physical cell layout and wire routing and then generates information for fabricating an IC die which implements the gate-level description.
Most commonly, the technology-independent description is written in a hardware description language (xe2x80x9cHDLxe2x80x9d) such as Very High-Speed IC (VHSIC) HDL, or xe2x80x9cVHDLxe2x80x9d. Typically, HDL code provides a well-defined, highly structured syntax for describing a system. Moreover, HDL permits signal processing functionality to be described without specifying the specific hardware required to implement the processing. Many aspects of writing HDL code have been treated in depth in the literature, such as in xe2x80x9cVHDL For Designersxe2x80x9d, S. Sjoholm and L. Lindh, Prentice Hall, 1997; xe2x80x9cVHDL And AHDLxe2x80x94Digital System Implementationxe2x80x9d, F. Scarpino, Prentice Hall 1998; and xe2x80x9cVHDLxe2x80x94Analysis and Modeling of Digital Systemsxe2x80x9d, Z. Navabi, McGraw-Hill 1998. These references are incorporated by reference herein as though set forth in full.
VHDL, in particular, allows a designer to describe a system using a functional description (e.g., using a hierarchical arrangement of interconnected functional components), a behavioral description (e.g., using sequential program statements that are similar to those of a high-level programming language), a data-flow description (e.g., using synchronous and asynchronous state machines, data paths, arithmetic operators, and registers), which may include register transfer level (RTL) description, a logic level description (e.g., using Boolean algebra), or by using any combination of these different description types. VHDL provides a syntax which is very similar to that of a software programming language and includes basic design components (or design entities) that have well-defined inputs and outputs. More complicated components can be designed from these basic design components in much the same way that complicated functions are created from basic functions in software design. Once created, these new components can be re-used and employed in hierarchical designs.
Because HDL generally describes a system in terms of generic functionality without specifying particular electronic components, HDL is referred to herein, and frequently in the current literature as well, as being xe2x80x9ctechnology independentxe2x80x9d. In fact, however, those skilled in the art do not understand the term xe2x80x9ctechnology-independentxe2x80x9d in its most strictly literal sense. The mere fact that the HDL description is designed with a view toward implementation on an IC, rather than in some other technology (such as optical computing), often will influence how the description is structured. Moreover, in certain cases a particular HDL description can be tailored to some extent for a given family of technology. Therefore, as used herein, the term xe2x80x9ctechnology-independentxe2x80x9d is intended to mean that the description is not primarily linked to a particular hardware implementation. Accordingly, when creating a technology-independent description, the designer generally can ignore factors such as driving strength, component choice, fanout and, often, the more detailed timing considerations.
During the synthesis phase of the IC design cycle, the HDL code is mapped to actual electronic components selected from an available technology library, together with interconnections between those components. Typically, synthesis is performed using an automated software tool such as Design Compiler, produced by Synopsis, Inc. Therefore, synthesis of HDL code in IC design is often likened to compilation of source code in software development.
Gate-level synthesis is thus the first step of IC design in which actual physical components are specified. In order to maintain a feasible design, the actual physical properties of these components generally must be considered. For instance, gate-level synthesis typically considers factors such as gate delay, power consumption and driving strength. In addition, the physical properties of wires connecting the various electronic components also should be considered. In fact, as chip design has improved and as gates have become increasingly faster, wire delays have become even more critical than gate delays in IC design. In this regard, it has been estimated that as much as 70 to 80% of the total delay in certain integrated circuits is due to wire delay. However, as indicated above, the precise routing of a wire between any two electronic components ordinarily is not determined until the physical design phase, and therefore typically is not known during gate-level synthesis.
As a result, many conventional synthesis techniques use a generic wire load model and a generic wire area model for estimating wire capacitance and resistance, respectively. Specifically, the conventional generic wire models typically do not distinguish between wires routed on different metal layers, but rather use a single model which is applied to all metal layers. In fact, however, different metal layers ordinarily will have different distances from the semiconductor substrate, different spacings from adjacent metal layers, and different thicknesses. As a result, electrical properties often will vary according to the metal layer used. Because a generic wire model is employed in the conventional techniques, these estimates frequently lack sufficient accuracy. Such conventional techniques often require either unnecessary error margins, which can increase the size or decrease the speed of the design or, alternatively, can result in additional errors which are discovered only later in the design cycle. In particular, subsequently discovered design problems often require repeating earlier steps to correct the problem, thus increasing the overall cost and time required to design the IC.
Based on the foregoing observation, applicants have filed co-pending U.S. patent application No. 09/007,242, titled xe2x80x9cImproved Method Of Selecting And Synthesizing Metal Interconnect Wires In Integrated Circuitsxe2x80x9d, which application is incorporated herein by reference as though set forth herein in full. In application number 09/007,242, applicants have proposed assigning metal layers to signals in the gate-level synthesis phase of IC design, so that it can be known during the synthesis phase which metal layer is to be used for routing a particular signal. Using this knowledge, more accurate estimates of actual wire capacitance and wire resistance often can be obtained.
However, as noted above gate-level synthesis is usually performed automatically using a software tool. Accordingly, assigning metal layer attributes during synthesis typically will not permit the designer to influence the selection of metal layers for particular signals. In addition, it might not always be convenient to assign metal layer attributes during synthesis.
It is therefore an object of the invention to address the foregoing problem by utilizing a technology-independent description of a system that specifies both a signal and a metal layer attribute for the signal.
According to one aspect, the invention is directed to design of an electronic circuit to be implemented on an integrated circuit die which includes several metal layers, in which a technology-independent description of a system is generated, the technology-independent description specifying a signal and a selected metal layer for the signal.
According to a further aspect, the invention is directed to design of an electronic circuit to be implemented on an integrated circuit die having several metal layers. A hardware description language (HDL) description of a system is generated, the HDL description specifying a signal and a selected metal layer for the signal. An electronic circuit description of the system is then synthesized from the HDL description of the system generated in said generating step, the electronic circuit description of the system specifying electronic components, an interconnection between two of the electronic components, and further specifying that the interconnection between the two electronic components is to be routed on the selected metal layer, the interconnection between the two electronic components corresponding to the signal specified in the generating step.
By virtue of the foregoing arrangement, when creating a technology-independent description of a system a user is capable of designating particular metal layers for routing particular signals. Because the user generally will be aware of the differing properties of the different metal layers, the user often will be able to more accurately tailor the design to the specific requirements of individual signals. For example, the user often knows that a particular signal will require a short delay time; utilizing the foregoing arrangement, the user can designate the metal layer for that signal accordingly. Moreover, in certain cases it may be more convenient for the designer to specify metal layer attributes during design of the technology-independent description of the system, when signal requirements are a significant concern.
In a still further aspect, the invention is directed to synthesizing an electronic circuit description of a system from a technology-independent description of the system. A technology-independent description of the system is input, the technology-independent description specifying a signal and a metal layer attribute for the signal. Electronic components are selected from a library based on the technology-independent description and interconnections between the electronic components are specified. A metal layer is then specified for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.
By virtue of the foregoing arrangement, synthesis of the electronic circuit description can be carried out in consideration of which metal layer is being utilized for a certain electrical connection. As a result, calculations made during such synthesis often can be performed more accurately. For instance, wire capacitance and wire resistance often vary from one metal layer to the next. Utilizing layer-specific characteristics, together with a designation indicating on which metal layer a certain electrical connection is to be made, more accurate estimations of the connection""s delay and electrical resistance often can be obtained. Consequently, tighter error margins often can be utilized, resulting in more efficient overall designs. Moreover, because a metal layer attribute for the signal is included in the technology-independent description, assigning metal layer attributes during synthesis often can be avoided.
The foregoing summary is intended merely to provide a brief description of the general nature of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.